USRP Hardware Driver and USRP Manual  Version: 4.1.0.4-3
UHD and USRP Manual
constants.hpp
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1 //
2 // Copyright 2014 Ettus Research LLC
3 // Copyright 2018 Ettus Research, a National Instruments Company
4 //
5 // SPDX-License-Identifier: GPL-3.0-or-later
6 //
7 
8 #pragma once
9 
10 #include <uhd/rfnoc/defaults.hpp>
11 #include <uhd/types/dict.hpp>
12 #include <stdint.h>
13 #include <boost/assign/list_of.hpp>
14 #include <string>
15 
16 namespace uhd { namespace rfnoc {
17 
18 constexpr uint16_t RFNOC_PROTO_VER = 0x0100;
19 
20 static const size_t NOC_SHELL_COMPAT_MAJOR = 5;
21 static const size_t NOC_SHELL_COMPAT_MINOR = 1;
22 
23 static const size_t MAX_PACKET_SIZE = 8000; // bytes
24 static const size_t DEFAULT_PACKET_SIZE = 1456; // bytes
25 
26 // One line in FPGA is 64 Bits
27 static const size_t BYTES_PER_LINE = 8;
28 
30 static const size_t DEFAULT_FC_XBAR_RESPONSE_FREQ = 8;
32 static const size_t DEFAULT_FC_RX_RESPONSE_FREQ = 64; // ACKs per flow control window
34 static const size_t DEFAULT_FC_TX_RESPONSE_FREQ = 8; // ACKs per flow control window
36 // Why not 100% full? Because we need to have some headroom to account for the inaccuracy
37 // when computing the window size. We compute the flow control window based on the frame
38 // size but the buffer can have overhead due to things like UDP headers, page alignment,
39 // housekeeping info, etc. This number has to be transport agnostic so 20% of headroom is
40 // safe.
41 static const double DEFAULT_FC_RX_SW_BUFF_FULL_FACTOR = 0.80;
42 
43 // Common settings registers.
44 static const uint32_t SR_FLOW_CTRL_BYTES_PER_ACK = 1;
45 static const uint32_t SR_FLOW_CTRL_WINDOW_SIZE = 2;
46 static const uint32_t SR_FLOW_CTRL_EN = 3;
47 static const uint32_t SR_ERROR_POLICY = 4;
48 static const uint32_t SR_BLOCK_SID = 5; // TODO rename to SRC_SID
49 static const uint32_t SR_NEXT_DST_SID = 6;
50 static const uint32_t SR_RESP_IN_DST_SID = 7;
51 static const uint32_t SR_RESP_OUT_DST_SID = 8;
52 static const uint32_t SR_FLOW_CTRL_PKT_LIMIT = 9;
53 
54 static const uint32_t SR_READBACK_ADDR = 124;
55 static const uint32_t SR_READBACK = 127;
56 
57 static const uint32_t SR_CLEAR_RX_FC = 125;
58 static const uint32_t SR_CLEAR_TX_FC = 126;
59 
64  SR_READBACK_REG_FIFOSIZE = 2, // fifo size
69 };
70 
71 // AXI stream configuration bus (output master bus of axi wrapper) registers
72 static const uint32_t AXI_WRAPPER_BASE = 128;
73 static const uint32_t AXIS_CONFIG_BUS =
74  AXI_WRAPPER_BASE + 1; // tdata with tvalid asserted
75 static const uint32_t AXIS_CONFIG_BUS_TLAST =
76  AXI_WRAPPER_BASE + 2; // tdata with tvalid & tlast asserted
77 
78 static const size_t CMD_FIFO_SIZE = 256; // Lines == multiples of 8 bytes
79 static const size_t MAX_CMD_PKT_SIZE = 3; // Lines == multiples of 8 bytes
80 
81 // Named settings registers
82 static const uhd::dict<std::string, uint32_t> DEFAULT_NAMED_SR =
83  boost::assign::map_list_of("AXIS_CONFIG_BUS", AXIS_CONFIG_BUS)(
84  "AXIS_CONFIG_BUS_TLAST", AXIS_CONFIG_BUS_TLAST);
85 
86 // Blocks
87 static const size_t MAX_NUM_BLOCKS = 16;
88 
89 // Block ports
90 static const size_t ANY_PORT = size_t(~0);
91 static const size_t MAX_NUM_PORTS = 16;
92 
93 // Regular expressions
94 static const std::string VALID_BLOCKNAME_REGEX = "[A-Za-z][A-Za-z0-9_]*";
95 static const std::string VALID_BLOCKID_REGEX =
96  "(?:(\\d+)(?:/))?([A-Za-z][A-Za-z0-9]*)(?:(?:#)(\\d\\d?))?";
97 
98 }} /* namespace uhd::rfnoc */
Definition: dict.hpp:22
constexpr uint16_t RFNOC_PROTO_VER
Definition: constants.hpp:18
settingsbus_reg_t
Settings register readback.
Definition: constants.hpp:61
@ SR_READBACK_REG_MTU
Definition: constants.hpp:65
@ SR_READBACK_REG_BLOCKPORT_SIDS
Definition: constants.hpp:66
@ SR_READBACK_REG_ID
Definition: constants.hpp:62
@ SR_READBACK_COMPAT
Definition: constants.hpp:68
@ SR_READBACK_REG_FIFOSIZE
Definition: constants.hpp:64
@ SR_READBACK_REG_USER
Definition: constants.hpp:67
@ SR_READBACK_REG_GLOBAL_PARAMS
Definition: constants.hpp:63
Definition: build_info.hpp:12